Silicon compute

Why silicon won.

A semiconductor conducts electricity better than an insulator and worse than a metal, and, more usefully, how well it conducts can be set by the material and switched by an electric field. That controllability is the whole basis of a transistor. Silicon is not the fastest semiconductor, and it was not the first one used: the first transistor, built at Bell Labs in 1947, was germanium.

Silicon won on three properties that matter more at scale than raw speed. Its bandgap of 1.12 electron-volts is wide enough that it does not leak badly when warm, and narrow enough to switch at low voltage. It is abundant: about a quarter of the Earth's crust by mass, mined as quartz. And it grows its own oxide. Heat silicon in oxygen and you get silicon dioxide, a near-perfect insulator with a clean interface to the crystal underneath. Germanium's oxide dissolves in water. That one difference is why the MOS transistor, demonstrated in 1959, was built on silicon.

Pure silicon is almost useless electrically. It is made useful by doping: adding a tiny fraction of other atoms. Phosphorus or arsenic, with one more outer electron than silicon, give n-type material with spare electrons. Boron, with one fewer, gives p-type material with "holes" that behave like positive charges. Every transistor is built from regions of the two placed side by side.

Bandgap

1.12 eV at room temperature

Share of Earth's crust

About 28% by mass

Electronic-grade purity

9 to 11 nines (99.9999999%+)

Crystal structure

Diamond cubic

Melting point

1,414 °C

A transistor is a switch with no moving parts.

The device inside almost every digital chip is the MOSFET: metal oxide semiconductor field-effect transistor. It has four parts. A source and a drain are doped regions where current enters and leaves. Between them sits the channel. Above the channel, separated from it by a very thin insulating layer, is the gate.

With no voltage on the gate, the channel does not conduct and the switch is off. Raise the gate above the threshold voltage and the field pulls carriers into a thin layer at the surface of the channel. Current now flows from source to drain and the switch is on. An n-type transistor turns on when its gate goes high. A p-type transistor does the opposite and turns on when its gate goes low.

A perfect switch would pass no current when off, plenty when on, and flip instantly using almost no charge. Real ones fall short in a way that has shaped the whole industry. Below threshold, current does not stop; it falls by roughly ten times for every 60 millivolts the gate drops, at room temperature. That limit comes from the thermal spread of electron energies, not from engineering, so it cannot be designed away in a conventional transistor. It sets a floor on how low the supply voltage can go before an "off" switch leaks too much.

How the gate got better

As the gate shrank, its insulating oxide thinned to a few atoms and electrons began tunnelling straight through it. The fix, in volume production from 2007, was high-k metal gate: replace silicon dioxide with a hafnium-based insulator that can be physically thicker while still coupling the gate strongly to the channel. Before that, from around 2003, strained silicon had stretched or squeezed the crystal so carriers move faster. Both are still in every leading-edge transistor.

Pairs of switches make logic.

CMOS, complementary MOS, builds every logic gate from n-type and p-type transistors working as a pair. In the simplest gate, the inverter, a p-type transistor connects the output to the supply and an n-type transistor connects it to ground. A high input turns the n-type on and the p-type off, so the output goes low; a low input does the reverse.

The point of the pairing is that in either steady state one of the two transistors is off, so there is no direct path from supply to ground. A CMOS gate draws real power only while it is switching. That property is why CMOS displaced every other logic family in the 1980s, and why a phone can hold billions of transistors without melting.

The power a chip burns while switching follows a simple rule: activity, times capacitance, times the square of the voltage, times frequency. Voltage is squared, so lowering it is by far the strongest lever a designer has. That is why the leakage floor from lesson 02 matters so much: it stops voltage falling further.

1. TransistorOne switch
2. Logic gateNAND, NOR, inverter
3. Adder, registerArithmetic and state
4. DatapathALU, pipeline
5. CoreFetch, decode, execute
6. ChipCores, caches, I/O

Memory on the die

The fast memory on a processor, its caches and register files, is SRAM. A standard SRAM bit is six transistors: two inverters feeding each other hold the value, and two access transistors read and write it. SRAM is fast and needs no refreshing, but six transistors per bit is expensive in area. In recent nodes, SRAM cells have shrunk more slowly than logic, so caches take a growing share of the die. That is one reason designers now stack cache on a separate die (course 03 covers how).

Scaling, and what broke.

In 1965 Gordon Moore observed that the number of components on a chip was doubling every year, and in 1975 he revised the pace to every two years. Moore's law is an economic observation, not a law of physics: it holds only as long as someone pays to make it hold.

For about thirty years it came with a second, quieter rule. Dennard scaling (1974) showed that if you shrink a transistor's dimensions and its voltage by the same factor, it gets faster and its power density stays constant. Each new node therefore gave more transistors, at higher clock speed, in the same power budget.

Dennard scaling ended in the mid-2000s, because voltage could no longer fall without leakage running away. Clock speeds stalled in the 3 to 5 GHz range, where they still sit. The industry kept adding transistors but spent them differently: first on more cores, then on specialised hardware such as GPUs and AI accelerators that do one kind of work far more efficiently than a general-purpose core.

Node names are labels

Process names such as "5 nm", "3 nm" or "18A" stopped describing any physical dimension in the late 1990s. They are product names for a generation. A "3 nm" process has a gate pitch of around 45 to 50 nanometres and its tightest metal lines in the low 20s. To compare processes, look at the numbers below rather than at the name.

Contacted gate pitch

Spacing between transistor gates

Minimum metal pitch

Spacing of the tightest wires

Logic density

Millions of transistors per mm²

SRAM bitcell area

µm² per bit of cache

Power and speed

At a stated voltage, against a stated baseline

The transistor changed shape to keep shrinking.

A short gate struggles to switch its channel fully off, because the drain's field reaches under it. The answer each time has been to wrap the gate around more of the channel, so the gate rather than the drain has control.

Power from below

For decades both the signal wires and the power wires sat above the transistors, competing for the same space. Backside power delivery moves power to the underside of the thinned wafer, so the front is left for signals. That frees routing space and cuts voltage loss. It reached volume production in 2025 and is on every leading manufacturer's roadmap.

Beyond CFET, the channel itself may change. Silicon gets worse when it is only a few atoms thick, so research groups are building channels from two-dimensional materials such as molybdenum disulfide. Course 05 picks this up.

The walls compute runs into.

Transistors still get denser, but the limits on a modern chip are mostly somewhere else. Four of them shape almost every design decision made today.

The responses are the themes of the rest of this academy: specialised chips (course 04), chiplets and advanced packaging with memory stacked beside or on top of logic (course 03), smaller number formats such as 8-bit and 4-bit floating point for AI, and new physics for the jobs silicon does worst (course 05).

How to read a compute number.

Headline figures are quoted in FLOP/s (floating-point operations per second) or TOPS (trillions of operations per second, usually integer). On their own they mean little. Three questions turn one into something you can compare.

• At what precision? A chip may do twice the operations at 8-bit as at 16-bit, and twice again at 4-bit. FP64 for science, FP32 and BF16 for training, FP8 and FP4 for inference are not interchangeable.
• Dense or sparse? Many datasheets quote figures that assume half the weights are zero in a fixed pattern. That doubles the headline, and most workloads do not get it.
• Fed by what? Peak compute is only reachable if memory can supply the data. Check memory bandwidth (TB/s), capacity, and the chip-to-chip link.

The roofline

A workload's arithmetic intensity is the number of operations it does per byte it moves. The speed you can actually reach is the lower of two numbers: peak compute, or memory bandwidth times arithmetic intensity. A chip with 1,000 TFLOP/s and 4 TB/s of bandwidth needs 250 operations per byte to stay busy. Below that, the workload is memory-bound and extra compute sits idle. Generating text one token at a time with a large language model is a common example.

Peak compute

1,000 TFLOP/s

Memory bandwidth

4 TB/s

Ridge point

1,000 ÷ 4 = 250 FLOP per byte

Workload at 50 FLOP/byte

Reaches 200 TFLOP/s, 20% of peak